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ht86bxx/ht86brxx enhanced voice 8-bit mcu rev. 1.70 1 february 22, 2010 general description the voice type series of mcus are 8-bit high perfor- mance microcontrollers which include a voice synthe- sizer and tone generator. they are designed for applications which require multiple i/os and sound ef- fects, such as voice and melody. the devices can pro- vide various sampling rates and beats, tone levels, tempos for speech synthesizer and melody generator. they also include an integrated high quality, voltage type dac output. the external interrupt can be trig - gered with falling edges or both falling and rising edges. the devices are excellent solutions for versatile voice and sound effect product applications with their efficient mcu instructions providing the user with programming capability for powerful custom applications. the system frequency can be up to 8mhz at an operating voltage of 2.2v and include a power-down function to reduce power consumption. device types devices which have the letter br within their part number, indicate that they are otp devices offering the advantages of easy and effective program updates, us- ing the holtek range of development and programming tools. these devices provide the designer with the means for fast and low-cost product development cy- cles. devices which have the letter b within their part number indicate that they are mask version devices. these devices offer a complementary device for appli - cations that are at a mature state in their design process and have high volume and low cost demands. part numbers including r are otp devices, all others are mask version devices. fully pin and functionally compatible with their otp sis - ter devices, the mask version devices provide the ideal substitute for products which have gone beyond their development cycle and are facing cost-down demands. in this datasheet, for convenience, when describing de - vice functions, only the otp types are mentioned by name, however the same described functions also ap - ply to the mask type devices. features operating voltage: 2.2v~5.5v system clock: 4mhz~8mhz crystal and rc system oscillator 16/20/24 i/o pins 8k 16-bit program memory 1928/384 8-bit data memory external interrupt input three 8-bit programmable timers with overflow interrupt and 8-stage prescaler 12-bit high quality voltage type d/a output pwm circuit direct audio output external rc oscillator converter 8 capacitor/resistor sensor input watchdog timer function 8-level subroutine nesting low voltage reset function integrated voice rom with various capacities power-down function and wake-up feature reduce power consumption up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v 63 powerful instructions technical document application note ha0075e mcu reset and oscillator circuits application note
selection table the devices include a comprehensive range of features, with most features common to all devices. the main features distinguishing them are program memory and data memory capacity, voice rom and voice capacity, i/o count, stack size and package types. the functional differences between the devices are shown in the following table. part no. vdd program memory data memory voice rom voice capacity i/o timer c/r-f d/a stack package types 8-bit 16-bit HT86B03 2.2v~5.5v 4k 16 192 8 96k 8 36sec 12 3 12-bit 8 16nsop, 24ssop (150/209mil) ht86br10 2.2v~5.5v 8k 16 192 8 192k 8 72sec 16 3 12-bit 8 24ssop(209mil), 28sop, 44qfp ht86b10 24ssop (150/209mil), 28sop, 44qfp ht86b20 2.2v~5.5v 8k 16 192 8 256k 8 96sec 16 3 12-bit 8 28sop, 44qfp ht86br30 2.2v~5.5v 8k 16 192 8 384k 8 144sec 16 3 12-bit 8 28sop, 44qfp ht86b30 ht86b40 2.2v~5.5v 8k 16 384 8 512k 8 192sec 20 3 1 12-bit 8 28sop, 44qfp ht86b50 2.2v~5.5v 8k 16 384 8 768k 8 288sec 20 3 1 12-bit 8 28sop, 44qfp ht86br60 2.2v~5.5v 8k 16 384 8 1024k 8 384sec 20 3 1 12-bit 8 28sop ht86b60 28sop, 44qfp ht86b70 2.2v~5.5v 8k 16 384 8 1536k 8 576sec 24 3 1 12-bit 8 44/100qfp ht86b80 2.2v~5.5v 8k 16 384 8 2048k 8 768sec 24 3 1 12-bit 8 44/100qfp ht86b90 2.2v~5.5v 8k 16 384 8 3072k 8 1152sec 24 3 1 12-bit 8 100qfp note: 1. for devices that exist in more than one package formats, the table reflects the situation for the larger package. 2. for the ht86b90, the operating voltage is 2.2v~5.5v at f sys =4mhz/3.3v~5.5v at f sys =8mhz. 3. voice length is estimated by 21k-bit data rate block diagram ht86bxx/ht86brxx rev. 1.70 2 february 22, 2010
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pin assignment ht86bxx/ht86brxx rev. 1.70 3 february 22, 2010 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + . + + / + + 0 , 1 , , + , , , -, ., , /, , 0- 1 - - +- ,- -
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pad assignment HT86B03 chip size: 1975 1930 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86bxx/ht86brxx rev. 1.70 4 february 22, 2010 / . - , + 1 * $ *
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5 1 6 1 7 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + . 3
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ht86br10 chip size: 3265 4010 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86bxx/ht86brxx rev. 1.70 5 february 22, 2010 5 1 6 1 7 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + . + / + + 0 , 1 , , + , , . - , + 1 2 1 2 2 + 3
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ht86b10 chip size: 1975 2640 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86bxx/ht86brxx rev. 1.70 6 february 22, 2010 5 1 6 1 7 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + . + + / + + 0 , 1 , , + , , / . - , + 1 2 1 2 2 + 3
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ht86br30 chip size: 4280 4330 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86bxx/ht86brxx rev. 1.70 7 february 22, 2010 5 1 6 1 7 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + . , , + , , . - , + 1 2 1 2 2 + 3
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ht86b20/ht86b30 chip size: 1975 3300 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86bxx/ht86brxx rev. 1.70 8 february 22, 2010 5 1 6 1 7 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + . + + / + + 0 , 1 , , + , , / . - , + 1 2 1 2 2 + 3
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ht86b40 chip size: 1975 3970 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86bxx/ht86brxx rev. 1.70 9 february 22, 2010 5 1 6 1 7 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + . + + / + + 0 , 1 , , + , , / . - , + 1 2 1 2 2 + 3
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ht86br60 chip size: 4290 8835 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86bxx/ht86brxx rev. 1.70 10 february 22, 2010 5 1 6 1 7 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + . , , + , , . - , + 1 2 1 2 2 + 3
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ht86b50/ht86b60 chip size: 1975 5725 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86bxx/ht86brxx rev. 1.70 11 february 22, 2010 5 1 6 1 7 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + . + + / + + 0 , 1 , , + , , / . - , + 1 2 1 2 2 + 3
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ht86b70/ht86b80 chip size: 3615 4940 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86bxx/ht86brxx rev. 1.70 12 february 22, 2010 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + 0 , 1 , , + / . - , + 1 2 1 2 2 + 3
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ht86b90 chip size: 3620 6700 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht86bxx/ht86brxx rev. 1.70 13 february 22, 2010 + , - . / 0 1 + , - . / 0 + 1 + + + + , + - + 0 , 1 , , + / . - , + 1 2 1 2 2 + 3
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pad coordinates HT86B03 unit: m pad no. x y pad no. x y 1 879.400 236.700 14 46.350 816.900 2 784.400 236.700 15 51.150 816.900 3 839.400 428.200 16 154.150 816.900 4 839.400 523.200 17 294.450 833.650 5 839.400 626.200 18 368.450 833.650 6 839.400 721.200 19 442.450 833.650 7 839.400 824.200 20 516.450 833.650 8 632.350 816.900 21 839.390 592.550 9 537.350 816.900 22 839.390 488.250 10 434.350 816.900 23 839.390 321.808 11 339.350 816.900 24 839.390 218.358 12 236.350 816.900 25 737.790 1 16.308 13 141.350 816.900 ht86br10 unit: m pad no. x y pad no. x y 1 1483.900 1900.000 18 779.500 1856.400 2 1483.900 838.050 19 682.500 1856.400 3 1483.900 933.050 20 521.245 1860.845 4 1483.900 1036.050 21 447.245 1860.845 5 1483.900 1131.050 22 373.245 1860.845 6 1483.900 1234.050 23 299.245 1860.845 7 1483.900 1329.050 24 1478.900 1821.650 8 1483.900 1432.050 25 1478.900 1700.550 9 1483.900 1527.050 26 1478.900 1605.550 10 1483.900 1630.050 27 1442.800 1497.530 11 1474.850 1856.400 28 1442.800 1395.130 12 1379.850 1856.400 29 1442.800 1295.470 13 1276.850 1856.400 30 1439.405 1162.343 14 1181.850 1856.400 31 1442.395 1024.550 15 1078.850 1856.400 32 1442.395 814.050 16 983.850 1856.400 33 1442.395 683.200 17 881.645 1856.400 34 1468.400 1879.850 ht86bxx/ht86brxx rev. 1.70 14 february 22, 2010
ht86b10 unit: m pad no. x y pad no. x y 1 839.400 189.100 18 45.150 1171.900 2 839.400 284.100 19 50.850 1171.900 3 839.400 387.100 20 153.850 1171.900 4 839.400 482.100 21 294.450 1188.650 5 839.400 585.100 22 368.450 1188.650 6 839.400 680.100 23 442.450 1188.650 7 839.400 783.100 24 516.450 1188.650 8 839.400 878.100 25 838.940 945.650 9 839.400 981.100 26 838.940 843.250 10 839.400 1076.100 27 802.900 704.400 11 839.400 1179.100 28 802.900 601.500 12 632.150 1171.900 29 802.900 504.300 13 537.150 1 171.900 30 792.250 351.400 14 434.150 1171.900 31 803.900 218.050 15 339.150 1171.900 32 803.900 7.550 16 236.150 1171.900 33 803.900 112.000 17 141.150 1171.900 ht86br30 unit: m pad no. x y pad no. x y 1 1991.400 1030.120 18 1152.895 2016.400 2 1991.400 1133.120 19 1055.695 2016.400 3 1991.400 1228.120 20 913.745 2016.400 4 1991.400 1331.120 21 709.506 2015.810 5 1991.400 1426.120 22 635.506 2015.810 6 1991.400 1529.120 23 561.506 2015.810 7 1991.400 1624.120 24 487.506 2015.810 8 1991.400 1727.120 25 1984.750 2016.500 9 1991.400 1822.120 26 1984.750 1921.500 10 1991.400 1925.120 27 1941.835 1711.230 11 1991.400 2020.120 28 1941.835 1586.960 12 1771.750 2016.400 29 1941.835 1487.300 13 1668.750 2016.400 30 1946.850 1363.920 14 1573.750 2016.400 31 1946.850 1233.070 15 1470.750 2016.400 32 1946.850 1022.570 16 1375.750 2016.400 33 1946.850 891.720 17 1251.695 2016.780 ht86bxx/ht86brxx rev. 1.70 15 february 22, 2010
ht86b20/ht86b30 unit: m pad no. x y pad no. x y 1 839.400 519.100 18 45.150 1501.900 2 839.400 614.100 19 50.850 1501.900 3 839.400 717.100 20 153.850 1501.900 4 839.400 812.100 21 294.450 1518.650 5 839.400 915.100 22 368.450 1518.650 6 839.400 1010.100 23 442.450 1518.650 7 839.400 1113.100 24 516.450 1518.650 8 839.400 1208.100 25 838.940 1275.650 9 839.400 1311.100 26 838.940 1173.250 10 839.400 1406.100 27 802.900 1034.400 11 839.400 1509.100 28 802.900 931.500 12 632.150 1501.900 29 802.900 834.300 13 537.150 1501.900 30 792.250 681.400 14 434.150 1501.900 31 803.900 548.050 15 339.150 1501.900 32 803.900 337.550 16 236.150 1501.900 33 803.900 218.000 17 141.150 1501.900 ht86b40 unit: m pad no. x y pad no. x y 1 839.400 701.930 20 44.500 1836.900 2 839.400 804.930 21 149.650 1836.900 3 839.400 899.930 22 255.250 1836.900 4 839.400 1002.930 23 359.150 1836.900 5 839.400 1097.930 24 462.150 1836.900 6 839.400 1200.930 25 619.850 1853.600 7 839.400 1295.930 26 693.850 1853.600 8 839.400 1398.930 27 767.850 1853.600 9 839.400 1493.930 28 841.850 1853.600 10 839.400 1596.930 29 839.390 1551.700 11 848.700 1836.900 30 839.390 1449.300 12 745.700 1836.900 31 802.900 1311.300 13 650.700 1836.900 32 802.900 1207.800 14 547.700 1836.900 33 802.900 1103.500 15 452.700 1836.900 34 792.350 959.450 16 349.700 1836.900 35 803.900 829.350 17 254.700 1836.900 36 803.900 618.850 18 153.500 1836.900 37 803.900 499.300 19 50.500 1836.900 ht86bxx/ht86brxx rev. 1.70 16 february 22, 2010
ht86br60 unit: m pad no. x y pad no. x y 1 1996.400 3279.080 20 954.350 4269.280 2 1996.400 3382.080 21 853.150 4269.280 3 1996.400 3477.080 22 753.150 4268.900 4 1996.400 3580.080 23 657.150 4268.900 5 1996.400 3675.080 24 515.200 4268.900 6 1996.400 3778.080 25 345.100 4268.850 7 1996.400 3873.080 26 271.100 4268.850 8 1996.400 3976.080 27 197.100 4268.850 9 1996.400 4074.580 28 123.100 4268.850 10 1996.400 4177.580 29 1991.750 4269.000 11 1996.400 4272.580 30 1991.750 4174.000 12 1750.825 4269.280 31 1948.850 3963.730 13 1655.825 4269.280 32 1948.850 3839.460 14 1552.825 4269.280 33 1948.850 3739.800 15 1457.825 4269.280 34 1953.850 3616.420 16 1354.825 4269.280 35 1953.850 3485.570 17 1259.825 4269.280 36 1953.850 3275.070 18 1152.350 4269.280 37 1953.850 3144.220 19 1049.350 4269.280 ht86b50/ht86b60 unit: m pad no. x y pad no. x y 1 839.400 1579.430 20 44.600 2714.400 2 839.400 1682.430 21 149.650 2714.400 3 839.400 1777.430 22 255.250 2714.400 4 839.400 1880.430 23 359.150 2714.400 5 839.400 1975.430 24 462.150 2714.400 6 839.400 2078.430 25 619.850 2731.100 7 839.400 2173.430 26 693.850 2731.100 8 839.400 2276.430 27 767.850 2731.100 9 839.400 2371.430 28 841.850 2731.100 10 839.400 2474.430 29 839.390 2427.100 11 848.700 2714.400 30 839.390 2326.800 12 745.700 2714.400 31 802.900 2188.800 13 650.700 2714.400 32 802.900 2085.300 14 547.700 2714.400 33 802.900 1981.000 15 452.700 2714.400 34 792.350 1836.950 16 349.700 2714.400 35 803.900 1706.850 17 254.700 2714.400 36 803.900 1496.350 18 153.400 2714.400 37 803.900 1376.800 19 50.400 2714.400 ht86bxx/ht86brxx rev. 1.70 17 february 22, 2010
ht86b70/ht86b80 unit: m pad no. x y pad no. x y 1 1659.400 1342.900 22 431.055 2321.900 2 1659.400 1437.900 23 328.055 2321.900 3 1659.400 1540.900 24 233.055 2321.900 4 1659.400 1635.900 25 130.855 2321.900 5 1659.400 1738.900 26 32.865 2321.900 6 1659.400 1833.900 27 67.140 2321.900 7 1659.400 1936.900 28 170.140 2321.900 8 1659.400 2031.900 29 332.095 2327.150 9 1659.400 2134.900 30 406.095 2327.150 10 1659.400 2229.900 31 480.095 2327.150 11 1659.400 2332.900 32 554.095 2327.150 12 1419.255 2321.900 33 1658.950 2324.995 13 1324.255 2321.900 34 1658.950 2229.995 14 1221.255 2321.900 35 1576.095 2087.795 15 1126.255 2321.900 36 1495.595 1979.695 16 1023.255 2321.900 37 1495.595 1869.845 17 928.255 2321.900 38 1623.910 1774.245 18 825.255 2321.900 39 1623.910 1640.895 19 730.255 2321.900 40 1623.910 1430.395 20 627.255 2321.900 41 1623.910 1310.845 21 532.255 2321.900 ht86b90 unit: m pad no. x y pad no. x y 1 1661.900 2222.900 22 433.555 3201.900 2 1661.900 2317.900 23 330.555 3201.900 3 1661.900 2420.900 24 235.555 3201.900 4 1661.900 2515.900 25 133.355 3201.900 5 1661.900 2618.900 26 35.365 3201.900 6 1661.900 2713.900 27 64.640 3201.900 7 1661.900 2816.900 28 167.640 3201.900 8 1661.900 2911.900 29 329.595 3207.150 9 1661.900 3014.900 30 403.595 3207.150 10 1661.900 3109.900 31 477.595 3207.150 11 1661.900 3212.900 32 551.595 3207.150 12 1421.755 3201.900 33 1656.900 3204.995 13 1326.755 3201.900 34 1493.095 2859.695 14 1223.755 3201.900 35 1573.595 2967.795 15 1128.755 3201.900 36 1656.900 3109.995 16 1025.755 3201.900 37 1493.095 2749.845 17 930.755 3201.900 38 1621.410 2654.245 18 827.755 3201.900 39 1621.410 2520.895 19 732.755 3201.900 40 1621.410 2310.395 20 629.755 3201.900 41 1621.410 2190.845 21 534.755 3201.900 ht86bxx/ht86brxx rev. 1.70 18 february 22, 2010
pin description HT86B03/ht86b10/ht86b20/ht86b30/ht86br10/ht86br30 pad name i/o options description pa0~pa7 i/o wake-up, pull-high or none bidirectional 8-bit i/o port. software instructions determined the cmos out - put or schmitt trigger with a pull-high resistor (determined by option). pb0~pb7 i/o pull-high or none bidirectional 8-bit i/o port. software instructions determined the cmos out - put or schmitt trigger with a pull-high resistor (determined by option). the HT86B03 device only has pb4~pb7 port pins. aud o audio output for driving an external transistor or for driving ht82v733 pwm1 pwm2 o audio pwm outputs. the HT86B03 has no pwm outputs. res i schmitt trigger reset input. active low. int i falling edge trigger or falling/rising edge trigger external interrupt schmitt trigger input without pull-high resistor. a configura - tion option determines if the interrupt active edge is a falling edge only or both a falling and rising edge. falling edge triggered active on a high to low transi - tion. rising edge triggered active on a low to high transition. input voltage is the same as operating voltage. osc1 osc2 crystal or rc osc1, osc2 are connected to an external rc network or external crystal, determined by configuration option, for the internal system clock. if the rc system clock option is selected, pin osc2 can be used to measure the sys - tem clock at 1/4 frequency. vdd positive digital power supply vss negative digital power supply, ground. vdda positive dac circuit power supply vssa negative dac circuit power supply, ground. vddp positive audio pwm circuit power supply vssp negative audio pwm circuit power supply, ground. note: 1. each pin on pa can be programmed through a configuration option to have a wake-up function. 2. individual pins can be selected to have pull-high resistors. ht86bxx/ht86brxx rev. 1.70 19 february 22, 2010
ht86b40/ht86b50/ht86b60/ht86br60 pad name i/o options description pa0~pa7 i/o wake-up, pull-high or none bi-directional 8-bit i/o port. software instructions determined the cmos out - put or schmitt trigger with a pull-high resistor (determined by option). pb0~pb7/ k0~k7 i/o pull-high or none bi-directional 8-bit i/o port. software instructions determined the cmos out - put or schmitt trigger with a pull-high resistor (determined by option). pins pb0~pb7 are pin-shared with c/r-f input pins k0~k7. pd4/rcout pd5/rr pd6/rc pd7/cc i/o pull-high or none bi-directional 4-bit i/o port. software instructions determined the cmos out - put or schmitt trigger with a pull-high resistor (determined by option). pins pd4~pd7 are pin-shared with r/f osc input pins rr, rc and cc. rcout: capacitor or resistor connection pin to rc osc for input. rr: oscillation input pin rc: reference resistor connection pin for output cc: reference capacitor connection pin for output aud o audio output for driving an external transistor or for driving ht82v733 pwm1 pwm2 o audio pwm outputs res i schmitt trigger reset input. active low. int i falling edge trigger or falling/rising edge trigger external interrupt schmitt trigger input without pull-high resistor. a configura - tion option determines if the interrupt active edge is a falling edge only or both a falling and rising edge. falling edge triggered active on a high to low transi - tion. rising edge triggered active on a low to high transition. input voltage is the same as operating voltage. osc1 osc2 crystal or rc osc1, osc2 are connected to an external rc network or external crystal, determined by configuration option, for the internal system clock. if the rc system clock option is selected, pin osc2 can be used to measure the sys- tem clock at 1/4 frequency. vdd positive digital power supply vss negative digital power supply, ground. vdda positive dac circuit power supply vssa negative dac circuit power supply, ground. vddp positive audio pwm circuit power supply vssp negative audio pwm circuit power supply, ground. note: 1. each pin on pa can be programmed through a configuration option to have a wake-up function. 2. individual pins can be selected to have pull-high resistors. ht86bxx/ht86brxx rev. 1.70 20 february 22, 2010
ht86b70/ht86b80/ht86b90 pad name i/o options description pa0~pa7 i/o wake-up, pull-high or none bi-directional 8-bit i/o port. software instructions determined the cmos out - put or schmitt trigger with a pull-high resistor (determined by option). pb0~pb7/ k0~k7 i/o pull-high or none bi-directional 8-bit i/o port. software instructions determined the cmos out - put or schmitt trigger with a pull-high resistor (determined by option). pins pb0~pb7 are pin-shared with c/r-f input pins k0~k7. pd0~pd3 pd4/rcout pd5/rr pd6/rc pd7/cc i/o pull-high or none bi-directional 8-bit i/o port. software instructions determined the cmos out - put or schmitt trigger with a pull-high resistor (determined by option). pins pd4~pd7 are pin-shared with r/f osc input pins rr, rc and cc. rcout: capacitor or resistor connection pin to rc osc for input. rr: oscillation input pin rc: reference resistor connection pin for output cc: reference capacitor connection pin for output aud o audio output for driving an external transistor or for driving ht82v733 pwm1 pwm2 o audio pwm outputs res i schmitt trigger reset input. active low. int i falling edge trigger or falling/rising edge trigger external interrupt schmitt trigger input without pull-high resistor. a configura - tion option determines if the interrupt active edge is a falling edge only or both a falling and rising edge. falling edge triggered active on a high to low transi - tion. rising edge triggered active on a low to high transition. input voltage is the same as operating voltage. osc1 osc2 crystal or rc osc1, osc2 are connected to an external rc network or external crystal, determined by configuration option, for the internal system clock. if the rc system clock option is selected, pin osc2 can be used to measure the sys- tem clock at 1/4 frequency. vdd positive digital power supply vss negative digital power supply, ground. vdda positive dac circuit power supply vssa negative dac circuit power supply, ground. vddp positive audio pwm circuit power supply vssp negative audio pwm circuit power supply, ground. note: 1. each pin on pa can be programmed through a configuration option to have a wake-up function. 2. individual pins can be selected to have pull-high resistors. absolute maximum ratings supply voltage ...........................v ss +2.2v to v ss +5.5v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ht86bxx/ht86brxx rev. 1.70 21 february 22, 2010
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz/8mhz 2.2 5.5 v f sys =4mhz for ht86b90 only 2.2 5.5 v f sys =8mhz for ht86b90 only 3.3 5.5 v i dd operating current 3v no load, f sys =4mhz, dac/pwm disable 1.5 ma 5v 5ma 3v no load, f sys =8mhz, dac/pwm disable 3ma 5v 7ma i stb1 standby current (wdt off) 3v no load, system halt wdt disable 1 a 5v 2 a i stb2 standby current (wdt on) 3v no load, system halt wdt enable 7 a 5v 10 a v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v il3 input low voltage for ext int 0 0.3v dd v v ih3 input high voltage for ext int 0.7v dd v dd v v lvr low voltage reset lvr 2.2v option 2.1 2.2 2.3 v i ol1 i/o port sink current 3v v ol =0.1v dd 4 ma 5v 10 ma i oh1 i/o port source current 3v v oh =0.9v dd 2 ma 5v 5 ma i ol2 rc and cc sink current 3v v ol =0.1v dd 4 ma 5v 10 ma i oh2 rc and cc source current 3v v oh =0.9v dd 2 ma 5v 5 ma i ol3 pwm1/pwm2 sink current 3v v ol =0.1v dd 50 ma 5v 80 ma i oh3 pwm1/pwm2 source current 3v v oh =0.9v dd 14.5 ma 5v 26 ma i aud aud source current 3v v oh =0.9v dd 1.5 ma 5v 3 ma r ph pull-high resistance 3v 20 60 100 k
5v 10 30 50 k
ht86bxx/ht86brxx rev. 1.70 22 february 22, 2010
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (rc osc, crystal osc) 2.2v~5.5v 4 8 mhz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 *t sys t lvr low voltage reset time 2 ms t int interrupt pulse width 1 s t mat circumscribe memory access time 2.2v~5.5v 400 ns note: *t sys =1/f sys characteristics curves ht86brxx r vs. f chart characteristics curves t vs. f chart characteristics curves ht86bxx/ht86brxx rev. 1.70 23 february 22, 2010 ! " 8 9 & 5 : ; 7 5 7 - + . 1 0 . + . , / - - . 1 , < 1 * - < . * 5
7 =
=
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v vs. f chart characteristics curves 3.0v v vs. f chart characteristics curves 4.5v ht86bxx r vs. f chart characteristics curves ht86bxx/ht86brxx rev. 1.70 24 february 22, 2010 # ! " $ % ! # & 8 9 & 5 : ; 7 * 5 * 7 + - + < , < 1 , < , , < - < + - < . - < 0 . < + . < . + < + - : ; + . : ; 0 . : ; . 1 1 # ! " $ % !
# & 8 9 & 5 : ; 7 * 5 * 7 + < + + < , < 1 , < - < + - < . . < + . < . , < , - < 0 - + - : ; + / - : ; 0 1 : ; - . 1 ! " 8 9 & 5 : ; 7 5 7 - + + / + 1 1 , < 1 * - < . *
t vs. f chart characteristics curves v vs. f chart characteristics curves 3.0v v vs. f chart characteristics curves 4.5v ht86bxx/ht86brxx rev. 1.70 25 february 22, 2010 5
7 =
=
5 + .
7 1 < 0 + 1 < 0 - 1 < 0 1 < 0 < 1 1 < 1 + < 1 - 1 - 1 + 1 1 + 1 - 1 1 1 1 1 * > . * * > , * * > , * * > . * ! " # ! " $ % ! # & 8 9 & 5 : ; 7 * 5 * 7 + - + < , < 1 , < , , < - < + - < . - < 0 . < + . < . - : ; + . : ; : ; / + < + # ! " $ % !
# & 8 9 & 5 : ; 7 * 5 * 7 + < + + < , < 1 , < - < + - < . . < + . < . , < , - < 0 - + - : ; + / : ; : ;
ht86bxx/ht86brxx rev. 1.70 26 february 22, 2010 system architecture a key factor in the high-performance features of the holtek range of voice microcontrollers is attributed to the internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it car - ries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the inter - nal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o, voltage type dac, pwm direct drive output, capacitor/resistor sensor input and external rc oscillator converter with maximum reli - ability and flexibility. clocking and pipelining the main system clock, derived from either a crystal/ resonator or rc oscillator is subdivided into four inter- nally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. when the rc oscillator is used, osc2 is freed for use as a t1 phase clock synchronizing pin. this t1 phase clock has a frequency of f sys /4 with a 1:3 high/low duty cycle. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. 8 ! < 5
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ht86bxx/ht86brxx rev. 1.70 27 february 22, 2010 program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call , that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is se - lected. however, it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be in- serted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writable. the activated level is indexed by the stack pointer, sp, and is neither readable nor writable. at a subroutine call or interrupt acknowledge signal, the con - tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, sig - naled by a return instruction, ret or reti , the pro - gram counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. mode program counter *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000000 external interrupt 0000000000100 timer 0 overflow 0000000001000 timer 1 overflow 0000000001100 timer 2 overflow 0000000010000 timer 3 overflow 0000000010100 skip program counter + 2 loading pcl *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *12~*0: program counter bits s12~s0: stack register bits #12~#0: instruction code bits @7~@0: pcl bits the program counter in the HT86B03 is only 12-bits wide therefore the *12 column in the table is not applicable. #
& ( % ( % + ( % , ( % # ' = 2 =
ht86bxx/ht86brxx rev. 1.70 28 february 22, 2010 if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions: arithmetic operations add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. by using the appropriate pro - gramming tools, this program memory device offer us - ers the flexibility to conveniently debug and develop their applications while also offering a means of field programming. organization the program memory stores the program instructions that are to be executed. it also includes data, table and interrupt entries, addressed by the program counter along with the table pointer. the program memory size is 8192 16 bits. certain locations in the program mem - ory are reserved for special usage. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execu - tion. location 004h this vector is used by the external interrupt. if the ex - ternal interrupt pin on the device goes low, the pro - gram will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 008h this internal vector is used by the 8-bit timer 0. if a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. location 00ch this internal vector is used by the 8-bit timer1. if a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. location 010h for the ht86b40, ht86b50, ht86b50, ht86b60, ht86br60, ht86b70, ht86b80, ht86b90 devices, this internal vector is used by the 16-bit timer2. if a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. location 014h this internal vector is used by the 8-bit timer3. if a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. 8 8 8 : 1 . : 1 1 1 : 1 1 - : 1 1 : 1 1
: 1 1 : % * 4 ? % & ' * % * 4 ? % & ' * 1 & ' * 1 - : 1 & ' * & ' * & ' * + & ' * , & ' * , & ' *
% * 4 ? % & ' * 1 & ' * & ' * , & ' * 8 8 8 : program memory structure
ht86bxx/ht86brxx rev. 1.70 29 february 22, 2010 look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, table pointers are used to setup the address of the data that is to be accessed from the program memory. however, as some devices pos - sess only a low byte table pointer and other devices pos - sess both a high and low byte pointer it should be noted that depending upon which device is used, accessing look-up table data is implemented in slightly different ways. for the devices, there are two table pointer registers known as tblp and tbhp in which the lower order and higher order address of the look-up data to be retrieved must be respectively first written. unlike the other de - vices in which only the low address byte is defined using the tblp register, the additional tbhp register allows the complete address of the look-up table to be defined and consequently allow table data from any address and any page to be directly accessed. for these de - vices, after setting up both the low and high byte table pointers, the table data can then be retrieved from any area of program memory using the tabrdc [m] in - struction or from the last page of the program memory using the tabrdl [m] instruction. when either of these instructions are executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the following diagram illustrates the addressing/data flow of the look-up table for the devices: table program example the following example shows how the table pointer and table data is defined and retrieved from the devices. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 1f00h which re - fers to the start address of the last page within the pro - gram memory of the microcontroller. the table pointer is setup here to have an initial value of 06h . this will en - sure that the first data read from the data table will be at the program memory address 1f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the tabrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] instruction is exe- cuted. # 2 ( 2 ( : ' = " c d : # ! 2 = %
( ) 2 = %
2 : look-up table tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 1f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address 1f05h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org 1f00h ; sets initial address of ht86b60 last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
ht86bxx/ht86brxx rev. 1.70 30 february 22, 2010 because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter - rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. instruction table location *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 11111@7@6@5@4@3@2@1@0 table location note: *12~*0: current program rom table p12~p8: write p12~p8 to tbhp pointer register @7~@0: write @7~@0 to tblp pointer register for the HT86B03, the table address location is 12-bits, that is from bit 0 to bit 11. data memory the data memory is a volatile area of 8-bit wide ram in - ternal memory and is the location where temporary in - formation is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to di- rectly under program control, however, some remain protected from user manipulation. the second area of ram data memory is reserved for general purpose use. all locations within this area are read and write accessi- ble under program control. organization the data memory is subdivided into two banks, known as bank 0 and bank 1, all of which are implemented in 8-bit wide ram. most of the ram data memory is lo - cated in bank 0 which is also subdivided into two sec - tions, the special purpose data memory and the general purpose data memory. the length of these sections is dictated by the type of microcontroller cho - sen. the start address of the ram data memory for all devices is the address 00h , and the last data memory address is ffh . registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the ' % & ' 1 1 : 8 8 : + : e % & ' 5 0 + 2 7 b $ ) 1 1 : - 1 : 8 8 : , 0 : ' % & ' e % & ' 5 0 + 2 7 - 1 :
2 2 - 1 : 8 8 : 2 1 ram data memory structure bank 0, bank1 note: most of the ram data memory bits can be directly manipulated using the set [m].i and clr [m].i instruc - tions with the exception of a few dedicated bits. the ram data memory can also be accessed through the memory pointer registers mp0 and mp1.
ht86bxx/ht86brxx rev. 1.70 31 february 22, 2010 set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. special purpose data memory this area of data memory, is located in bank 0, where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h . although the special purpose data memory registers are located in bank 0, they will still be accessible even if the bank pointer has selected bank 1. special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the ram data memory area. these registers ensure correct op - eration of internal functions such as timers, interrupts, watchdog, etc., as well as external functions such as i/o data control. the location of these registers within the ram data memory begins at the address 00h . any unused data memory locations between these special function registers and the point where the general pur- pose memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00h. indirect addressing register iar0, iar1 the indirect addressing registers, iar0 and iar1, al - though having their locations in normal ram register space, do not actually physically exist as normal regis - ters. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory ad - dressing, where the actual memory address is speci - fied. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corre - sponding memory pointer, mp0 or mp1. acting as a pair, iar0 and mp0 can together only access data from bank 0, while the iar1 and mp1 register pair can ac - cess data from both bank 0 and bank 1. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indi - rectly will result in no operation. memory pointer mp0, mp1 for all devices, two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers pro - viding a convenient way with which to address and track data. when any operation to the relevant indirect ad - dressing registers is carried out, the actual address that the microcontroller is directed to, is the address speci - fied by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0 only, while mp1 and iar1 are used to access data from both bank 0 and bank 1. the following example shows how to clear a section of four ram locations already defined as locations adres1 to adres4. 1 1 : 1 : 1 + : 1 , : 1 - : 1 . : 1 : 1 / : 1 : 1 0 : 1 : 1 2 : 1
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ht86bxx/ht86brxx rev. 1.70 32 february 22, 2010 data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses. bank pointer bp the ram data memory is divided into two banks, known as bank 0 and bank 1. with the exception of the bp register, all of the special purpose registers and general purpose registers are contained in bank 0. if data in bank 0 is to be accessed, then the bp register must be loaded with the value "00", while if data in bank 1 is to be accessed, then the bp register must be loaded with the value 01. using memory pointer mp0 and indirect addressing register iar0 will always access data from bank 0, irre- spective of the value of the bank pointer. the data memory is initialised to bank 0 after a reset, except for the wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within either bank 0 or bank 1. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro- grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple- mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per - mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tblh these two special function registers are used to control operation of the look-up table which is stored in the pro - gram memory. tblp is the table pointer and indicates the location where the table data is located. its value must be setup before any table read commands are ex - ecuted. its value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the ' ( % ) ' " * ! / 1 2 1 2 1 1 2 1 2 3 & " 6 & f 1 f bank pointer bp
ht86bxx/ht86brxx rev. 1.70 33 february 22, 2010 high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user de - fined location. watchdog timer register wdts the watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. to implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. to provide variable watchdog timer reset times, the watchdog timer clock source can be divided by various division ra - tios, the value of which is set using the wdts register. by writing directly to this register, the appropriate divi - sion ratio for the watchdog timer clock source can be setup. note that only the lower 3 bits are used to set divi - sion ratios between 1 and 128. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera- tions related to the status register may give different re- sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib - ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high - est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. interrupt control register intc, intch two 8-bit register, known as the intc and intch regis- ters, controls the operation of both external and internal timer interrupts. by setting various bits within these reg- isters using standard bit manipulation instructions, the enable/disable function of the external and timer inter- rupts can be independently controlled. a master inter- rupt bit within this register, the emi bit, acts like a global enable/disable and is used to set all of the interrupt en- able bits on or off. this bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the reti instruction. note: in situations where other interrupts may require servicing within present interrupt service rou - tines, the emi bit can be manually set by the pro - gram after the present interrupt service routine has been entered. 8 * g

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ht86bxx/ht86brxx rev. 1.70 34 february 22, 2010 timer registers depending upon which device is selected, all devices contain three or four integrated timers of either 8-bit or 16-bit size. all devices contain three 8-bit timers whose associated registers are known as tmr0, tmr1 and tmr3, which is the location where the associated timer's 8-bit value is located. their associated control registers, known as tmr0c, tmr1c and tmr3c, con - tain the setup information for these timers. some de - vices also contain an additional 16-bit timer whose register pair name is known as tmr2l/tmr2h and is the location where the timer's 16-bit value is located. an associated control register, known as tmr2c, contains the setup information for this timer. note that all timer registers can be directly written to in order to preload their contents with fixed data to allow different time inter - vals to be setup. input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pb, pd, etc. these la - beled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc, pdc, etc., also mapped to specific addresses with the data memory. the control register specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the con- trol register must be set high, for an output it must be set low. during program initialisation, it is important to first setup the control registers to specify which pins are out - puts and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits us - ing the set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice-versa by manipulating specific bits of the i/o control registers during normal program operation is a useful feature of these devices. voice rom data address latch counter registers these are the latch0h/latch0m/latch0l, latch1h/latch1m/latch1l and the voice rom data registers. the voice rom data address latch coun - ter provides the handshaking between the microcontroller and the voice rom, where the voice codes are stored. eight bits of voice rom data will be addressed by using the 22-bit address (except for the HT86B03 which has only 18-bits) latch counter, which is composed of latch0h/latch0m/latch0l or latch1h/latch1m/latch1l. after the 8-bit voice rom data is addressed, several instruction cycles of at least 4us at least, will be required to latch the voice rom data, after which the microcontroller can read the voice data from latchd. voice control and audio output registers voicec, dal, dah, vol the device includes a single 12-bit current type dac function for driving an external 8
speaker through an external npn transistor. the programmer must write the voice data to the dal/dah registers. pulse width modulator registers pwmc, pwml, pwmh each device contains a single 12-bit pwm function for driving an external 8
speaker. the programmer must write the voice data to pwml/pwmh register. analog switch registers ascr some devices, include 8 analog switch lines, which have an associated register, known as ascr, for their setup and control. external rc oscillation converter registers rcoccr, rcocr, tmr4l, tmr4h for the ht86b40/ht86b50/ht86b60/ht86br60/ ht86b70/ ht86b80/ht86b90 devices, which have two 16-bit programmable timers, the tmr4l and tmr4h registers are for one of the 16-bit timers. the rcoccr and rcocr registers are the control registers for the external rc oscillator.
ht86bxx/ht86brxx rev. 1.70 35 february 22, 2010 input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high op - tions for all ports and wake-up options on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. depending upon which device or package is chosen, the microcontroller range provides from 16 to 24 bidirectional input/output lines labeled with port names pa, pb, pd, etc. these i/o ports are mapped to the data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input oper - ation, these ports are non-latching, which means the in - puts must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains un - changed until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via configuration options and are implemented using a weak pmos transistor. note that if the pull-high option is selected, then all i/o pins on that port will be con- nected to pull-high resistors, individual pins can be se- lected for pull-high resistor options. port a wake-up each device has a halt instruction enabling the microcontroller to enter a power down mode and pre - serve power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. after a halt instruction forces the microcontroller into entering a halt condition, the processor will re - main idle or in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low. this function is especially suitable for applica - tions that can be woken up via external switches. note that each pin on port a can be selected individually to have this wake-up feature. i/o port control registers each i/o port has its own control register pac, pbc, pdc, etc., to control the input/output configuration. with this control register, each cmos output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be writ - ten as a 1 . this will then allow the logic state of the in - put pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over- come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro- gram control. analog switch for the ht86b40, ht86b50, ht86b60, ht86br60, ht86b70, ht86b80 and ht86b90 devices, pins pb0~pb7 are pin-shared with analog switch pins k0 to k7. the choice of which function is used is selected using configuration options and remains fixed after the device is programmed. external rc oscillator converter for the ht86b40, ht86b50, ht86b60, ht86br60, ht86b70, ht86b80 and ht86b90 devices, pins pd4~pd7 are pin-shared with external oscillator con - verter pins rcout, rr, rc and cc. the external rc oscillator converter function is selected via a configu - ration option and remains fixed after the device is pro - grammed. i/o pin structures the following diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional under - standing of the i/o pins. note also that the specified pins refer to the largest device package, therefore not all pins specified will exist on all devices.
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ht86bxx/ht86brxx rev. 1.70 37 february 22, 2010 programming considerations within the user program, one of the first things to con - sider is port initialization. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the port control registers, pac, pbc, pdc, etc., are then pro - grammed to setup some pins as outputs, these output pins will have an initial high output value unless the as - sociated port data registers, pa, pb, pd, etc., are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control reg - ister using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then re - write this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timers the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the devices in the voice type mcu series contain either three or four count up timers of either 8 or 16-bit capacity depending upon which de - vice is selected. the provision of an internal prescaler to the clock circuitry of some of the timer gives added range to the timer. there is single type of register related to the timer. the first is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the contents of the timer. all devices can have the timer clock configured to come from the internal clock source. the accompanying table lists the associated timer register names. HT86B03 ht86b10 ht86br10 ht86b20 ht86b30 ht86br30 ht86b40 ht86b50 ht86b60 ht86br60 ht86b70 ht86b80 ht86b90 no. of 8-bit timers 33 timer register name tmr0 tmr1 tmr3 tmr0 tmr1 tmr3 timer control register tmr0c tmr1c tmr3c tmr0c tmr1c tmr3c no. of 16-bit timers 1 timer register name tmr2l tmr2h timer control register tmr2c configuring the timer input clock source the clock source for the 8-bit timers is the system clock divided by four while the 16-bit timer has a choice of ei - ther the system clock or the system clock divided by four. the 8-bit timer clock source is also first divided by the division ratio of which is conditioned by the three lower bits of the associated timer control register. + , - + , - " =
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ht86bxx/ht86brxx rev. 1.70 38 february 22, 2010 timer registers tmr0, tmr1, tmr2l/tmr2h, tmr3 the timer registers are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. all devices con - tain three 8-bit timers, whose registers are known as tmr0, tmr1 and tmr3. the ht86b40, ht86b50, ht86b60, ht86br60, ht86b70, ht86b80 and ht86b90 devices also contain an additional single 16-bit timer, which has a pair of registers known as tmr2l and tmr2h. the value in the timer registers in - creases by one each time an internal clock pulse is re- ceived. the timer will count from the initial value loaded by the preload register to the full count of ffh for the 8-bit timer or ffffh for the 16-bit timers at which point the timer overflows and an internal interrupt signal is generated. the timer value will then be reset with the ini- tial preload register value and continue counting. note that to achieve a maximum full range count of ffh for the 8-bit timer or ffffh for the 16-bit timers, the preload registers must first be cleared to all zeros. it should be noted that after power-on, the preload regis - ters will be in an unknown condition. note that if the timer counters are in an off condition and data is writ - ten to their preload registers, this data will be immedi - ately written into the actual counter. however, if the counter is enabled and counting, any new data written into the preload data register during this period will re - main in the preload register and will only be written into the actual counter the next time an overflow occurs. note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, programmers must take this into account. for devices which have an internal 16-bit timer, and which therefore have both low byte and high byte timer registers, accessing these registers is carried out in a specific way. it must be noted that when using instruc - tions to preload data into the low byte register, namely tmr2l, the data will only be placed in a low byte buffer and not directly into the low byte register. the actual transfer of the data into the low byte register is only car - ried out when a write to its associated high byte register, namely tmr2h, is executed. however, using instruc - tions to preload data into the high byte timer register will result in the data being directly written to the high byte register. at the same time the data in the low byte buffer will be transferred into its associated low byte register. for this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. it must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer into its associated low byte register. after this has been done, the low byte register can be read in the normal way. note that reading the low byte timer register will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. timer control registers tmr0c, tmr1c, tmr2c, tmr3c each timer has its respective timer control register, known as tmr0c, tmr1c, tmr2c and tmr3c. it is the timer control register together with their correspond - ing timer registers that control the full operation of the timers. before the timers can be used, it is essential that the appropriate timer control register is fully pro - grammed with the right data to ensure its correct opera - tion, a process that is normally carried out during program initialization. bits 7 and 6 of the timer control register, which are known as the bit pair tm1/tm0 re - spectively, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as ton, depending upon which timer is used, provides the basic on/off control of the respective timer. setting the bit high allows the timer to run, clearing the bit stops the timer. for the 8-bit timers, which have prescalers, bits 0~2 of the timer control register deter - mine the division ratio of the input clock prescaler. "
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1 ,
1 1 1 1 1 b + b - b b b , + b - b + b + . timer control register all devices / 3 1 1 3 ' % " 6 " f 1 f
& # 4 % b % 1 b " % 3 * , ) " * ! 3 ' % " 6 " f 1 f ' # " % + 1 1 + 1 1 1 " % % " % % " " % % timer control register ht86b40/ht86b50/ht86b60/ht86br60/ht86b70/ht86b80/ht86b90 configuring the timer the timer is used to measure fixed time intervals, pro - viding an internal interrupt signal each time the timer overflows. to do this the operating mode select bit pair in the timer control register must be set to the correct value as shown. control register operating mode select bits bit7 bit6 10 the internal clock, f sys , is used as the timer clock. however, this clock source is further divided by a prescaler, the value of which is determined by the prescaler rate select bits, which are bits 0~2 in the timer control register. after the other bits in the timer control register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to enable the timer to run. each time an internal clock cy - cle occurs, the timer increments by one. when it is full and overflows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer interrupt en - able bit in the interrupt control register, intc, is reset to zero.
% % % & ' & @ @ + @ 3 @ 3 @ timer mode timing diagram
ht86bxx/ht86brxx rev. 1.70 40 february 22, 2010 prescaler all of the 8-bit timers possess a prescaler. bits 0~2 of their associated timer control register, define the pre-scaling stages of the internal clock source of the timer. the timer overflow signal can be used to gener - ate signals for the timer interrupt. programming considerations the internal system clock is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. in this mode, when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the pro - gram flow to the respective internal interrupt vector. when the timer is read, the clock is blocked to avoid er - rors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly ini - tialized before using them for the first time. the associ - ated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control regis - ter must also be correctly set to ensure the timer is prop - erly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer reg - isters are unknown. after the timer has been initialized the timer can be turned on and off by controlling the en - able bit in the timer control register. timer program example the following example program section is based on the ht86b40, ht86b50, ht86b60, ht86br60, ht86b70, ht86b80 and ht86b90 devices, which contain a single internal 16-bit timer. programming the timer for other de - vices is conducted in a very similar way. the program shows how the timer registers are setup along with how the interrupts are enabled and managed. points to note in the example are how, for the 16-bit timer, the low byte must be written first, this is because the 16-bit data will only be written into the actual timer register when the high byte is loaded. also note how the timer is turned on by setting bit 4 of the respective timer control register. the timer can be turned off in a similar way by clearing the same bit. this example program sets the timer to be in the timer mode which uses the internal system clock as their clock source. #include ht86b40.inc jmp begin : org 04h ; external interrupt vectors reti org 08h reti org 0ch reti org 10h ; timer 2 interrupt vector jmp tmr2int ; jump here when timer 2 overflows org 14h reti : ; internal timer 2 interrupt routine tmr2int: : ; timer 2 main program placed here : reti : begin: ; setup timer 2 registers mov a,09bh ; setup timer 2 low byte mov tmr2l,a ; low byte must be setup before high byte mov a,0e8h ; setup timer 2 high byte mov tmr2h,a ; setup timer 2 high byte mov a,090h ; setup timer 2 control register mov tmr2c,a ; setup timer mode ; setup interrupt register mov a,01h ; enable master interrupt mov intc,a mov a,01h ; enable timer 2 interrupt mov intch,a :
ht86bxx/ht86brxx rev. 1.70 41 february 22, 2010 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer requires microcontroller attention, their corresponding interrupt will enforce a temporary sus - pension of the main program allowing the microcontroller to direct attention to their respective needs. each device contains a single external interrupt and three or four internal timer interrupt functions. the external interrupt is controlled by the action of the exter - nal int pin, while the internal interrupt is controlled by the relevant timer overflow. interrupt register overall interrupt control, which means interrupt enabling and flag setting, is controlled using two registers, known as intc and intch, which are located in the data memory. by controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corre - sponding request flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation a timer overflow or the external interrupt line being pulled low will all generate an interrupt request by set- ting their corresponding request flag, if their appropriate interrupt enable bit is set. when this happens, the pro- gram counter, which stores the address of the next in- struction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the correspond - ing interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruc - tion at this vector will usually be a jmp statement which will take program execution to another section of pro - gram which is known as the interrupt service routine. here is located the code to control the appropriate inter - rupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original pro - gram counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the accompanying diagram with their order of priority. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou- tine, to allow interrupt nesting. if the stack is full, the in- terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. 4 * , ) " * ! / 1 4 1 4 4 4 4 8 1 8 4 8 & ' e % % 4 % b # % % % 1 b # % % " % 4 ? % & ' 4 % b % 1 b " % 1 & ' 4 % b % 1 b " % & ' 4 % b % 1 b " % 4 ? % & ' 9 & 8 % # b 1 b 1 & ' 9 & 8 % # b 1 b & ' 9 & 8 % # b 1 b 3 ' % " 6 " f 1 f interrupt control register
ht86bxx/ht86brxx rev. 1.70 42 february 22, 2010 4 * , ) " * ! 3 ' % " 6 " f 1 f / 1 4 + + & ' 4 % b % 1 b " % + & ' 9 & 8 % # b 1 b + 8 , 8 , & ' 4 % b % 1 b " % , & ' 9 & 8 % # b 1 b 4 , 3 ' % " 6 " f 1 f intch register & % %
% " & % %
% " = ) 4 ? % & ' 9 & 8 % # 4 8 4 4 4 & ' % % # : # ! & % % % "
4 % " & % % 1 & ' 9 & 8 % # 1 8 4 1 ( ) 4 , & ' 9 & 8 % # 8 4 , & ' 9 & 8 % # , 8 interrupt structure HT86B03/ht86b10/ht86br10/ht86b20/ht86b30/ht86br30 & % %
% " & % %
% " = ) 4 4 4 & ' % % # : # ! & % % % "
4 % " & % % 4 1 ( ) 4 + 4 4 , 1 & ' 9 & 8 % # 1 8 & ' 9 & 8 % # 8 + & ' 9 & 8 % # + 8 , & ' 9 & 8 % # , 8 4 ? % & ' 9 & 8 % # 4 8 interrupt structure ht86b40/ht86b50/ht86b60/ht86br60/ht86b70/ht86b80/ht86b90
ht86bxx/ht86brxx rev. 1.70 43 february 22, 2010 interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the accompanying table shows the priority that is applied. interrupt source interrupt vector HT86B03/ht86b10 ht86br10/ht86b20 ht86b30/ht86br30 priority ht86b40/ht86b50/ht86b60 ht86br60/ht86b70/ht86b80 ht86b90 priority external interrupt 04h 1 1 timer 0 overflow 08h 2 2 timer 1 overflow 0ch 3 3 timer 2 overflow 10h 4 timer 3 overflow 14h 4 5 in cases where both external and timer interrupts are enabled and where an external and timer interrupt occur simultaneously, the external interrupt will always have priority and will therefore be serviced first. suitable masking of the individual interrupts using the intc and intch registers can prevent simultaneous occur - rences. external interrupt each device contains a single external interrupt function controlled by the external pin, int . for an external inter- rupt to occur, the corresponding external interrupt en- able bit must be first set. this is bit 1 of the intc register and known as eei. an external interrupt is triggered by an external edge transition on the external interrupt pin int , after which the related interrupt request flag, eif, which is bit 4 of intc, will be set. a configuration option exists for the external interrupt pin to determine the type of external edge transition which will trigger an external interrupt. there are two options available, a low going edge or both high and low going edges. when the mas - ter interrupt and external interrupt bits are enabled, the stack is not full and an active edge transition, as setup in the configuration options, occurs on the int pin, a sub - routine call to the corresponding external interrupt vec - tor, which is located at 04h, will occur. after entering the interrupt execution routine, the corresponding interrupt request flag, eif, will be reset and the emi bit will be cleared to disable other interrupts. timer interrupt for a timer generated interrupt to occur, the correspond - ing timer interrupt enable bit must be first set. each de - vice contains three 8-bit timers whose corresponding interrupt enable bits are known as et0i, et1i and et3i and are located in the intc and intch registers. each timer also has a corresponding timer interrupt request flag, which are known as t0f, t1f and t3f, also located in the intc and intch registers. some devices also contain a 16-bit timer, which has a corresponding timer interrupt enable bit, et2i, and a corresponding timer re - quest flag, t2f, which are contained in the intch regis - ter. when the master interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and when the corresponding timer overflows a subrou - tine call to the corresponding timer interrupt vector will occur. the corresponding program memory vector loca- tions for timer 0, timer1, timer 2 and timer 3 are 08h, 0ch, 10h and 14h. after entering the interrupt execu- tion routine, the corresponding interrupt request flags, t0f, t1f, t2f or t3f will be reset and the emi bit will be cleared to disable other interrupts. programming considerations by disabling the interrupt enable bits, a requested inter- rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the intc or intch register until the corre - sponding interrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the con - tents of the register or status register are altered by the interrupt service program, which may corrupt the de - sired control sequence, then the contents should be saved in advance.
ht86bxx/ht86brxx rev. 1.70 44 february 22, 2010 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re- set operations result in different register conditions be- ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple- mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir- cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. 4 * & % 1 < 0 * power-on reset timing chart 4 1 < 8 1 1 * * 1 < 1 8 1 enhanced reset circuit 4 & % 1 < 0 * 1 < - * res reset timing chart 4 * * 1 < 8 1 1 basic reset circuit
ht86bxx/ht86brxx rev. 1.70 45 february 22, 2010 low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the bat - tery, the lvr will automatically reset the device inter - nally. the lvr includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. characteristics. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1. watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer all timer will be turned off prescaler the timer prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal regis - ters of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will reflect the situation for the larger package type. ( * & % low voltage reset timing chart & & % wdt time-out reset during normal operation timing chart & & wdt time-out reset during power down timing chart
ht86bxx/ht86brxx rev. 1.70 46 february 22, 2010 HT86B03 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out from halt mp0 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status 00 0000 1u uuuu uu uuuu 01 uuuu 11 uuuu intc 000 0000 000 0000 000 0000 000 0000 uuu uuuu tmr0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr0c 00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu tmr1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr1c 00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 uuuu pbc 1111 1111 1111 1111 uuuu tmr3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr3c 00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu intch 0 0 0 0 0 0 0 0 u u tbhp 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu dal 0000 uuuu uuuu uuuu uuuu dah 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu vol 000 0000 000 000 000 uuu voicec 0 00 0 00 0 00 0 00 u uu latch0h 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch0m 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch0l 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1h 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1m 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1l 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latchd 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu note: u stands for unchanged x stands for unknown stands for undefined
ht86bxx/ht86brxx rev. 1.70 47 february 22, 2010 ht86b10/ht86br10/ht86b20/ht86b30/ht86br30 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out from halt mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status 00 xxxx 1u uuuu uu uuuu 01 uuuu 11 uuuu intc 000 0000 000 0000 000 0000 000 0000 uuu uuuu tmr0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr0c 00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu tmr1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr1c 00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu tmr3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr3c 00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu intch 0 0 0 0 0 0 0 0 u u tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu dal xxxx uuuu uuuu uuuu uuuu dah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu vol xxx xxxx uuu uuuu uuu uuuu uuu uuuu uuu uuuu voicec 0 00 0 00 0 00 0 00 u uu latch0h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch0m xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1m xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latchd xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pwmc 0 0 00 0 00 0 00 0 0u u u pwml xxxx uuuu uuuu uuuu uuuu pwmh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu note: u stands for unchanged x stands for unknown stands for undefined
ht86bxx/ht86brxx rev. 1.70 48 february 22, 2010 ht86b40/ht86b50/ht86b60/ht86br60/ht86b70/ht86b80/ht86b90 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out from halt mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status 00 xxxx 1u uuuu uu uuuu 01 uuuu 11 uuuu intc 000 0000 000 0000 000 0000 000 0000 uuu uuuu tmr0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr0c 00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu tmr1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr1c 00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu tmr2h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr2l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr2c 00 0 00 0 00 0 00 0 uu u tmr3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr3c 00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu intch 00 00 00 00 00 00 00 00 uu uu tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu dal xxxx uuuu uuuu uuuu uuuu dah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu vol xxx xxxx uuu uuuu uuu uuuu uuu uuuu uuu uuuu voicec 0 00 0 00 0 00 0 00 u uu latch0h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch0m xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1m xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latchd xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
ht86bxx/ht86brxx rev. 1.70 49 february 22, 2010 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out from halt pwmc 0 0 00 0 00 0 00 0 0u u u pwml xxxx uuuu uuuu uuuu uuuu pwmh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ascr 1111 1111 1111 1111 uuuu rcoccr 0010 0010 0010 0010 uuuu tmr4h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr4l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu rcocr 1xxx 00 1xxx 00 1xxx 00 1xxx 00 uuuu uu note: u stands for unchanged x stands for unknown stands for undefined
ht86bxx/ht86brxx rev. 1.70 50 february 22, 2010 oscillator various oscillator options offer the user a wide range of functions according to their various application require - ments. two types of system clocks can be selected while various clock source options for the watchdog timer are provided for maximum flexibility. all oscillator options are selected through the configuration options. the two methods of generating the system clock are: external crystal/resonator oscillator external rc oscillator one of these two methods must be selected using the configuration options. more information regarding the oscillator is located in application note ha0075e on the holtek website. external crystal/resonator oscillator the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feed - back for oscillation, and will normally not require exter - nal capacitors. however, for some crystals and most resonator types, to ensure oscillation and accurate fre - quency generation, it may be necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specifica - tion. the external parallel feedback resistor, rp, is nor - mally not required but in some cases may be needed to assist with oscillation start up. internal ca, cb, rf typical values @ 5v, 25 c ca cb rf 11~13pf 13~15pf 800k
oscillator internal component values external rc oscillator using the external system rc oscillator requires that a resistorco. the mask mcu value between 60k
and 130k
, the otp mcu value between 150k
and 300k
. they connected between osc1 and vss. the generated system clock divided by 4 will be provided on osc2 as an output which can be used for external syn - chronization purposes. note that as the osc2 output is an nmos open-drain type, a pull high resistor should be connected if it to be used to monitor the internal fre - quency. although this is a cost effective oscillator config - uration, the oscillation frequency can vary with vdd, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are required. note that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. the external capacitor shown on the diagram does not influence the frequency of oscillation. watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65 sat5v requiring no external components. when the device en- ters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a configuration option.

+ = % & 4 ' " * ! ' 1 . ) 1 1 " % ! ) ! . 5 ) "

+

' 3 b < ' % % 9 & " < + < % ! & # ! ! )

+ ' ! ' ' = & " / ' 8 < crystal/resonator oscillator

+ = a - 3 ' external rc oscillator
ht86bxx/ht86brxx rev. 1.70 51 february 22, 2010 power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode, also known as the halt mode or sleep mode. when the device enters this mode, the nor - mal operating current, will be reduced to an extremely low standby current level. this occurs because when the device enters the power down mode, the system oscillator is stopped which reduces the power consump - tion to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requir - ing a full reset. this feature is extremely important in ap - plication areas where the mcu must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruc - tion in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the appli - cation program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source origi- nates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. special atten - tion must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. care must also be taken with the loads, which are connected to i/os, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the watchdog timer internal oscillator. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup via an individual config- uration option to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up oc- curs, the program will resume execution at the instruc- tion following the halt instruction. if the system is woken up by an interrupt, then two possi - ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe - cution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 1 be - fore entering the power down mode, the wake-up func - tion of the related interrupt will be disabled.
ht86bxx/ht86brxx rev. 1.70 52 february 22, 2010 no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 1024 system clock period delay has ended. watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the wdt counter overflows. the wdt clock is supplied by one of two sources selected by con - figuration option: its own self-contained dedicated inter - nal wdt oscillator, or the instruction clock which is the system clock divided by 4. note that if the wdt configu - ration option has been disabled, then any instruction re - lating to its operation will result in no operation. the internal wdt oscillator has an approximate period of 65 s at a supply voltage of 5v. if selected, it is first di - vided by 256 via an 8-stage counter to give a nominal period of 17ms. note that this period can vary with vdd, temperature and process variations. for longer wdt time-out periods the wdt prescaler can be utilized. by writing the required value to bits 0, 1 and 2 of the wdts register, known as ws0, ws1 and ws2, longer time-out periods can be achieved. with ws0, ws1 and ws2 all equal to 1, the division ratio is 1:128 which gives a maxi- mum time-out period of about 2.1s. a configuration option can select the instruction clock, which is the system clock divided by 4, as the wdt clock source instead of the internal wdt oscillator. if the in - struction clock is used as the clock source, it must be noted that when the system enters the power down mode, as the system clock is stopped, then the wdt clock source will also be stopped. therefore the wdt will lose its protecting purposes. in such cases the sys - tem cannot be restarted by the wdt and can only be re - started using external signals. for systems that operate in noisy environments, using the internal wdt oscillator is therefore the recommended choice. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. how - ever, if the system is in the power down mode, when a wdt time-out occurs, only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt and the wdt prescaler. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the wdt. note that for this second option, if clr wdt1 is used to clear the wdt, succes- sive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the wdt. similarly, after the clr wdt2 instruc- tion has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. + 6 * , ) " * ! / 1 ' % % + 1 1 1 1 1 1 1 1 1 1 1 1 1 b b + b - b b b , + b - b + 3 & " 1 watchdog timer register
ht86bxx/ht86brxx rev. 1.70 53 february 22, 2010 voice output voice control the voice control register controls the voice rom circuit and the dac circuit and selects the voice rom latch counter. if the dac circuit is not enabled, any dah/dal outputs will be invalid. writing a 1 to the dac bit will enable the enable dac circuit, while writing a 0 to the dac bit will disable the dac circuit. if the voice rom cir - cuit is not enabled, then voice rom data cannot be ac - cessed. writing a 1 to the vromc bit will enable the voice rom circuit, while writing a 0 to the vromc bit is will disable the voice rom circuit. the latch bit de- termines which voice rom address latch counter will be used as the voice rom address latch counter. audio output and volume control dal, dah, vol the audio output is 12-bits wide whose highest 8-bits are written into the dah register and whose lowest four bits are written into the highest four bits of the dal regis- ter. bits 0~3 of the dal register are always read as zero. there are 8 levels of volume which are setup using the vol register. only the highest 3-bits of this register are used for volume control, the other bits are not used and read as zero. voice rom data address latch counter the voice rom address is 22-bits wide (except for the HT86B03 which has only 10-bits) and therefore requires three registers to store the address. there are two sets of three registers to store this address, which are latch0h/latch0m/latch0l and latch1h/ latch1m/latch1l. the 22-bit address (except for the HT86B03 which has only 10-bits) stored in one set of these three registers is used to access the 8-bit voice code data in the voice rom. after the 8-bit voice rom data is addressed, a few instruction cycles, of at least 4us duration, are needed to latch the voice rom data. after this the microcontroller can read the voice data from the latchd register.
& 5 + . 7 / % $ h & 1 k +
% &
% '
= # & '
( 8 % #
( + 8 % # + &
(
( = a - % %
% &
= # & ' watchdog timer # 4 7 * , ) " * ! / 1 (
:
*

3 ' % " 6 " f 1 f
4 % b % 1 b " % * 4 % b % 1 b " % *
& % b " " ( ! 1 b " " ( ! 1 3 ' % " 6 " f 1 f 3 ' % " 6 " f 1 f voice control register / * , ) " * ! / 1 3 & " 6 " f 1 f , + 1 & " & ' & ) , ) " 1 " % ' 1 % , " / % 8 * , ) " * ! * , ) " * ! / 1 1 0 & " & ' & ) , ) " 1 " % ' 1 % , " ) , * , ) " * ! # % 1 5 - * % ' " ! % 1 * , ) " * ! / . - # / * , ) " * ! / 1 3 & " 6 " f 1 f % & % " * ( + * ( * ( 1 $ " & ' &
ht86bxx/ht86brxx rev. 1.70 54 february 22, 2010 example: read an 8-bit voice rom data which is located at address 000007h by address latch 0 set [26h].2 ; enable voice rom circuit mov a, 07h ; mov latch0l, a ; set latch0l to 07h mov a, 00h ; mov latch0m, a ; set latch0m to 00h mov a, 00h ; mov latch0h, a ; set latch0h to 00h call delay ; delay a short period of time mov a, latchd ; get voice data at 000007h pulse width modulation output all device include a single 12-bit pwm function. the pwm output is provided on two complimentary outputs on the pwm1 and pwm2 pins. these two pins can di - rectly drive a piezo buzzer or an 8 ohm speaker without requiring any external components. the pwm1 output can also be used alone to drive a piezo buzzer or an 8 ohm speaker without requiring external components. when the single pwm1 output is chosen, which is achieved by setting the single_pwm bit in the pwmc register. the pwm output will initially be at a low level, and if stopped will also return to a low level. if the pwmcc bit changes from low to high then the pwm function will start and latch new data. if the data is not updated then the old value will remain. if the pwmcc bit changes from high to low, at the end of the duty cycle, the pwm output will stop. 6 3 * , ) " * ! 1

# % m / 3 ' % " 6 " ; 4 % b % 1 b " % # % & ' & b # % & ' & 1 b " & % & ' & 3 ' % " 6 " ; pulse width modulator control register 6 3 / * , ) " * ! / 1 3 & " 6 " f 1 f , + 1 & ' & 5 1 * 6 ) 9 " 3 % 9 5 1 " % ! " / % 8 * , ) " * ! 6 3 * , ) " * ! / 1 1 0 & ' & 5 1 * 6 ) 9 " 3 % 9 5 1 " % ! " ) , * , ) " * ! / . - ' + 1 < 1 8 n 1 < 1 8 n f n f 8 " & # ! " # % ! & 6 " ' < 3 b / 1 # / * , ) " * ! 3 & " 6 " f 1 f % & % " * ( , * ( - * ( . * ( $ " & ' & * ( 1 1 1 1 1 1 1 * ( . 1 1 1 ? * ( - 1 1 1 ? * ( , 1 1 1 ? % & % % = ! & % & % & % % + % & % % , % & % % - % & % % . % & % % % & % % / % & % % = ! ? & % & volume control register
ht86bxx/ht86brxx rev. 1.70 55 february 22, 2010 external rc oscillation converter an external rc oscillation converter is implemented in certain devices and is a function which allows analog switch functions to be implemented. when used in con - junction with the analog switch function up to eight c/r-f can be implemented. external rc oscillation converter operation the rc oscillation converter is composed of two 16-bit count-up programmable timers. one is timer 2, de - scribed in the timer section and the other is an addi - tional counter known as timer 4. the rc oscillation converter is enabled when the rco bit, which is bit 1 of the rcocr register, is set high. the rc oscillation con - verter will then be composed of four registers, tmr2l, tmr2h, tmr4l and tmr4h. the timer 2 clock source comes from the system clock or from the system clock/4, the choice of which is determined by bits in the rcoccr register. the rc oscillation converter timer 4 clock source comes from an external rc oscillator. as the oscillation frequency is dependent upon external ca - pacitance and resistance values, it can therefore be used to detect the increased capacitance of a analog switch pad. there are six registers related to the rc oscillation con - verter. these are, tmr2h, tmr2l, rcoccr, tmr4h, tmr4l and rcocr. the internal timer clock is the in - put clock source for tmr2h and tmr2l, while the ex - ternal rc oscillator is the clock source input to tmr4h and tmr4l. the ovb bit, which is bit 0 of the rcocr register, decides whether the timer interrupt is sourced from either the timer 2 overflows or timer 4 overflow. when a timer overflow occurs, the t2f bit is set and an external rc oscillation converter interrupt occurs. when the rc oscillation converter timer 2 or timer 4 over - flows, the rcocon bit is automatically reset to zero and stops counting. the resistor and capacitor form an oscillation circuit and input to tmr4h and tmr4l. the rcom0, rcom1 and rcom2 bits of rcoccr define the clock source of timer 2. when the rcocon bit, which is bit 4 of the rcoccr register, is set high, timer 2 and timer 4 will start count - ing until timer 2 or timer 4 overflows. now the timer counter will generate an interrupt request flag which is bit t2f, bit 4 of the intch register. both timer 2 and timer 4 will then stop counting and the rcocon bit will automatically be reset to "0" at the same time. note that if the rcocon bit is high, the tmr2h, tmr2l, tmr4h and tmr4l registers cannot be read or written to. * , ) " * ! / 1 $ " = " 6 " ;
+

1

3
% %
4 % b 4 % 1 b % +
% & %
+ 1 1 1 b
1 1 b
1 1 1 b = a = a - b b $ " = " rcoccr register * , ) " * ! & ' & % b - = % ) 1 b + = % )

" b 4 % 1 b % / 1 $ " = " 6 " ;
* 2 rcocr register
ht86bxx/ht86brxx rev. 1.70 56 february 22, 2010 + -

3 * 2 > * 2 > 1 4 ? %
% %
& '

3

& ' & = a -
% % = a
2 programming considerations as the 16-bit timers have both low byte and high byte timer registers, accessing these registers is carried out in a specific way. it must be noted that when using in - structions to preload data into the low byte registers, namely tmr2l or tmr4l, the data will only be placed into a low byte buffer and not directly into the low byte register. the actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely tmr2h or tmr4h, is exe - cuted. however, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte register. at the same time the data in the low byte buffer will be transferred into its associated low byte register. for this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. it must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the con - tents of the low byte buffer into its associated low byte register. after this has been done, the low byte register can be read in the normal way. note that reading the low byte timer register will only result in reading the previ - ously latched contents of the low byte buffer and not the actual contents of the low byte timer register. program example external rc oscillation converter mode example program timer 2 overflow: clr rcoccr mov a, 00000010b ; enable external rc oscillation mode and set timer 2 ; overflow interrupt mov rcocr,a clr intch.4 ; clear external rc oscillation converter interrupt ; request flag mov a, low (65536-1000); give timer 2 initial value mov tmr2l, a ; timer 2 count 1000 time and then overflow mov a, high (65536-1000) mov tmr2h, a mov a, 00h ; give timer 4 initial value mov tmr4l, a mov a, 00h mov tmr4h, a mov a, 00110000b ; timer 2 clock source=fsys/4 and timer on mov rcoccr, a p10: clr wdt snz intch.4 ; polling external rc oscillation converter interrupt ; request flag jmp p10 clr intch.4 ; clear external rc oscillation converter interrupt ; request flag ; program continue
ht86bxx/ht86brxx rev. 1.70 57 february 22, 2010 analog switch there are 8 analog switch lines in the microcontroller, labeled as k0 ~ k7, and the analog switch control register, which is mapped to the data memory by option. all of these analog switch lines can be used together with the external rc oscillation converter for c/r-f input keys. * , ) " * ! % # ) ! % / 1 j 1 6 ! = = j 6 ! = = j + 6 ! = = j , 6 ! = = j - 6 ! = = j . 6 ! = = j 6 ! = = j / 6 ! = = % % = = 6
= = $ " = " 6 " ; 3 , 3 , 1 1 1 1 1 1 1 1 3 + 3 3 1 3 + 1 1 1 1 h 3 1 1 1 1 h 3 1 1 1 1 1 h analog switch control register ascr < e < + < e < , < e < - < e < . < e < < e < / j 1 j j + j , j - j . j j /
$

< e < 3 - < e < analog switch
ht86bxx/ht86brxx rev. 1.70 58 february 22, 2010 configuration options configuration options refer to certain options within the mcu that are programmed into the device during the program - ming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. no. HT86B03/ht86b10/ht86br10/ht86b20/ht86b30/ht86br30 options i/o options 1 pa0~pa7: wake-up enable or disable (bit option) 2 pa0~pa7: pull-high enable or disable (bit option) 3 pb0~pb7: pull-high enable or disable (bit option) - the HT86B03 device only has pb4~pb7 oscillation option 4 osc type selection: rc or crystal interrupt option 5 int triggering edge: falling or both watchdog options 6 wdt: enable or disable 7 wdt clock source: wdrosc or t1 8 clrwdt instructions: 1 or 2 instructions low voltage reset option 9 lvr select: enable or disable no. ht86b40/ht86b50/ht86b60/ht86br60/ht86b70/ht86b80/ht86b90 options i/o options 1 pa0~pa7: wake-up enable or disable 2 pa0~pa7: pull-high enable or disable 3 pb0~pb7: pull-high enable or disable 4 pd0~pd7: pull-high enable or disable 5 pb share pin select: pb0~7 or k0~7 6 pd share pin select: pd4~7 or external rc oscillation converter pin oscillation option 7 osc type selection: rc or crystal interrupt option 8 int triggering edge: falling or both watchdog options 9 wdt: enable or disable 10 wdt clock source: wdrosc or t1 11 clrwdt instructions: 1 or 2 instructions low voltage reset option 12 lvr select: enable or disable
application circuits HT86B03 ht86bxx/ht86brxx rev. 1.70 59 february 22, 2010 4 * * 3 1 1 * 1 < 8 1 1 8 * * * * 1 - / 8 1 < 8
+
1 k / 2 - k 2 / 4 * * 3 1 1 * 1 < 8 1 1 8
+
- : ; k : ; 1 k / 2 - k 2 / $ + , - . / # * - / 8 1 < 8 1 8 $ 3 * * 4 8 3
$
4 & " j 5 7 * 1 . 1 1 < 8 + j 5 7 $ ! ' ) " % ! 5 " 0 5 " % 8 * ! - 0 1 ) : ) * ! 5 " 0 5 " $
* * $ * * 1 - / 8 1 < 8
ht86b10/ht86br10/ht86b20/ht86b30/ht86br30 ht86bxx/ht86brxx rev. 1.70 60 february 22, 2010 4 * * 3 1 1 * 1 < 8 1 1 8 * * * * 1 - / 8 1 < 8
+
1 k / 2 1 k 2 / * * 4 * * 3 1 1 * 1 < 8 1 1 8
+
- : ; k : ; 1 k / 2 1 k 2 / * * * + $ + , - . / # * - / 8 1 < 8 1 8 $ 3 * * 4 8 3
$
4 & " j 5 7 * 1 . 1 1 < 8 + j 5 7 $ ! ' ) " % ! 5 " 0 5 " % 8 * ! - 0 1 ) : ) * ! 5 " 0 5 " $ j 5 7 3 b ! ' ' % = ! " ' = & % " ! " & % & ' & < - / 8 * * *

ht86b40/ht86b50/ht86b60/ht86br60 ht86bxx/ht86brxx rev. 1.70 61 february 22, 2010
4 * * 3 1 1 * 1 < 8 1 1 8 * * 1 - / 8 1 < 8
+ *
1 k / 2 1 k 2 / - k / * * * 4 * * 3 1 1 * 1 < 8 1 1 8
+
- : ; k : ; 1 k / 2 1 k 2 / * * *
- k / $ + , - . / # * - / 8 1 < 8 1 8 $ 3 * * 4 8 3
$
4 & " j 5 7 * 1 . 1 1 < 8 + j 5 7 $ ! ' ) " % ! 5 " 0 5 " % 8 * ! - 0 1 ) : ) * ! 5 " 0 5 " 3 b ! ' ' % = ! " ' = & % " ! " & % & ' & < $ + j 5 7 - / 8 * * *

ht86b70/ht86b80/ht86b90 ht86bxx/ht86brxx rev. 1.70 62 february 22, 2010 4 * * 3 1 1 * 1 < 8 1 1 8 * * 1 - / 8 1 < 8
+ *
1 k / 2 1 k 2 / 1 k / * * * 4 * * 3 1 1 * 1 < 8 1 1 8
+
- : ; k : ; 1 k / 2 1 k 2 / * * * 1 k / $ + , - . / # * - / 8 1 < 8 1 8 $ 3 * * 4 8 3
$
4 & " j 5 7 * 1 . 1 1 < 8 + j 5 7 $ ! ' ) " % ! 5 " 0 5 " % 8 * ! - 0 1 ) : ) * ! 5 " 0 5 " 3 b ! ' ' % = ! " ' = & % " ! " & % & ' & < $ + j 5 7 - / 8 * * *

ht86bxx/ht86brxx rev. 1.70 63 february 22, 2010 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht86bxx/ht86brxx rev. 1.70 64 february 22, 2010 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht86bxx/ht86brxx rev. 1.70 65 february 22, 2010 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht86bxx/ht86brxx rev. 1.70 66 february 22, 2010
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht86bxx/ht86brxx rev. 1.70 67 february 22, 2010
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht86bxx/ht86brxx rev. 1.70 68 february 22, 2010
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht86bxx/ht86brxx rev. 1.70 69 february 22, 2010
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht86bxx/ht86brxx rev. 1.70 70 february 22, 2010
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht86bxx/ht86brxx rev. 1.70 71 february 22, 2010
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht86bxx/ht86brxx rev. 1.70 72 february 22, 2010
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht86bxx/ht86brxx rev. 1.70 73 february 22, 2010
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht86bxx/ht86brxx rev. 1.70 74 february 22, 2010
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht86bxx/ht86brxx rev. 1.70 75 february 22, 2010
package information 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.335 0.346 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 8.51 8.79 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 ht86bxx/ht86brxx rev. 1.70 76 february 22, 2010 + - , + 2
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24-pin ssop (209mil) outline dimensions mo-150 symbol dimensions in inch min. nom. max. a 0.291 0.323 b 0.197 0.220 c 0.009 0.013 c 0.311 0.335 d 0.079 e 0.026 f 0.002 g 0.022 0.037 h 0.004 0.008 0 8 symbol dimensions in mm min. nom. max. a 7.40 8.20 b 5.00 5.60 c 0.22 0.33 c 7.90 8.50 d 2.00 e 0.65 f 0.05 g 0.55 0.95 h 0.09 0.21 0 8 ht86bxx/ht86brxx rev. 1.70 77 february 22, 2010 + - , + 2
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28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.697 0.713 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 17.70 18.11 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8 ht86bxx/ht86brxx rev. 1.70 78 february 22, 2010 + . - 2
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44-pin qfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.512 0.528 b 0.390 0.398 c 0.512 0.528 d 0.390 0.398 e 0.031 f 0.012 g 0.075 0.087 h 0.106 i 0.010 0.020 j 0.029 0.037 k 0.004 0.008 l 0.004 0 7 symbol dimensions in mm min. nom. max. a 13.00 13.40 b 9.90 10.10 c 13.00 13.40 d 9.90 10.10 e 0.80 f 0.30 g 1.90 2.20 h 2.70 i 0.25 0.50 j 0.73 0.93 k 0.10 0.20 l 0.10 0 7 ht86bxx/ht86brxx rev. 1.70 79 february 22, 2010 , - - - 2 + + + 4 8 e : o j , , + ,
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100-pin qfp (14mm 20mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.728 0.756 b 0.547 0.555 c 0.965 0.992 d 0.783 0.791 e 0.026 f 0.012 g 0.098 0.122 h 0.134 i 0.004 j 0.039 0.055 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 18.50 19.20 b 13.90 14.10 c 24.50 25.20 d 19.90 20.10 e 0.65 f 0.30 g 2.50 3.10 h 3.40 i 0.1 j 1.00 1.40 k 0.10 0.20 0 7 ht86bxx/ht86brxx rev. 1.70 80 february 22, 2010 1 1 1 . . 1 , , 1 2
4 8 e : o j
product tape and reel specifications reel dimensions ssop 24s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ht86bxx/ht86brxx rev. 1.70 81 february 22, 2010
2 +
carrier tape dimensions ssop 24s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.5 +0.25/-0.0 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 9.50.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.5 +0.25/-0.0 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 ht86bxx/ht86brxx rev. 1.70 82 february 22, 2010 1 4 8 j 1 2 1 1

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ht86bxx/ht86brxx rev. 1.70 83 february 22, 2010 copyright 2010 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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